This invention is directed to semiconductor memory devices and methods of making such devices, and more particularly, to non-volatile metal-insulator-semiconductor (MIS) memory elements having multiple insulating layers and methods of making said devices.
The earliest semiconductor memories were bipolar, usually transistor-transistor logic (TTL), and were very limited in the number of bits. With the development of the MOS technologies bit density has increased dramatically. At the present time N-channel MOS memories are being fabricated with 16,384 bits of memory per chip. However most of the memory devices available today are volatile, that is they lose the information stored in them when the power to the device is turned off. This disadvantage has led to efforts to create non-volatile semiconductor devices. Several non-volatile devices have been developed to meet this demand. One of them is described in U.S. Pat. No. 3,660,819. Another is described in U.S. Pat. No. 3,881,180. The MNOS device is another invention which offers a non-volatile memory. Such a device is described in Chang, Proceedings of the IEEE, Vol. 64, No. 7, July, 1976, pp. 1039-1059. However all of these devices have various disadvantages. Some of them require exposure to ultraviolet light to erase the information stored in the memory cells. Others are too large for high density designs. The MNOS while offering high density design capability and electrical erasure of stored information, requires high write/erase voltages and long write/erase times.
In copending U.S. patent application, Ser. No. 963,855, filed Nov. 27, 1978 (now U.S. Pat. No. 4,242,737) entitled "Non-volatile Semiconductor Memory Elements" by Robert T. Bate, a memory structure is disclosed which offers the advantages provided by so-called MNOS devices while substantially eliminating or reducing the effect of the disadvantages thereof, i.e. high write/erase voltages and long write/erase times.